--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--
-- DO NOT MODIFY THIS FILE
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mem_block is
	port (
		-- Port A
		a_clk : in std_logic;
		a_en : in std_logic;
		a_wr_en : in std_logic;
		a_addr : in std_logic_vector(8 downto 0);
		a_in : in std_logic_vector(15 downto 0);
		a_out : out std_logic_vector(15 downto 0);
		
		-- Port B
		b_clk : in std_logic;
		b_en : in std_logic;
		b_wr_en : in std_logic;
		b_addr : in std_logic_vector(8 downto 0);
		b_in : in std_logic_vector(15 downto 0);
		b_out : out std_logic_vector(15 downto 0)
	);
end mem_block;

architecture Behavioral of mem_block is
	-- BRAM Component
	component bram_prog_mem port (
		clka : in std_logic;
		ena : in std_logic;
		wea : in std_logic_vector(0 DOWNTO 0);
		addra : in std_logic_vector(8 DOWNTO 0);
		dina : in std_logic_vector(15 DOWNTO 0);
		douta : out std_logic_vector(15 DOWNTO 0);
		clkb : in std_logic;
		enb : in std_logic;
		web : in std_logic_vector(0 DOWNTO 0);
		addrb : in std_logic_vector(8 DOWNTO 0);
		dinb : in std_logic_vector(15 DOWNTO 0);
		doutb : out std_logic_vector(15 DOWNTO 0)
	); end component;
begin

	block_memory : bram_prog_mem port map (
		clka => a_clk,
		ena => a_en,
		wea(0) => a_wr_en,
		addra => a_addr,
		dina => a_in,
		douta => a_out,
		
		clkb => b_clk,
		enb => b_en,
		web(0) => b_wr_en,
		addrb => b_addr,
		dinb => b_in,
		doutb => b_out
	);

end Behavioral;

